Process-induced skew reduction in nominal zero-skew clock trees

Abstract — This work develops an analytic framework for clock tree analysis considering process variations that is shown to correspond well with Monte Carlo results. The analysis frame-work is used in a new algorithm that constructs deterministic nominal zero-skew clock trees that have reduced sensitivity to process variation. The new algorithm uses a sampling approach to perform route embedding during a bottom-up merging phase, but does not select the best embedding until the top-down phase. This results in clock trees that exhibit a mean skew reduction of 32.4 % on average and a standard deviation reduction of 40.7 % as verified by Monte Carlo. The average increase in total clock tree capacitance is less than 0.02%. I

Clock tree analysis and synthesis considering process parameters and variability.

Clock distribution is vital to all synchronous integrated circuits; a poor clock distribution network can result in limited speed, high power consumption, and non-functional circuits. As process dimensions continue to scale, clock distribution faces ever increasing numbers of clock sinks and increased uncertainty in physical and electrical parameters that can significantly limit the yield of manufactured chips. This thesis examines clock tree analysis and synthesis in the presence of process parameters and variation by introducing concepts in statistical analysis, clock tree routing, and clock tree buffer/wire tuning. The efficient statistical analysis techniques developed enable optimization to route and tune variation-aware clock trees. A discretized algorithm for robust clock routing is presented that considers nominally unequal metal layers in addition to metal variations. Then, after the routes are buffered for slew reliability, the buffers and wires are tuned to minimize skew and increase robustness with optional power constraints using heuristics in both the deterministic and statistical timing domain. A novel sensitivity-matching algorithm is presented that allows clock tree skews to be correlated with data-path sensitivies to ameliorate sensitivity to variation. The result from the contributions in this thesis is improved robustness of clock trees in the presence of process variation. Our methods of routing, deterministic tuning, and statistical tuning showed improvements of 32.4%, 24.1%, and 16.3%, respectively, in terms of expected clock skew over traditional algorithms.Ph.D.Applied SciencesComputer scienceElectrical engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/126162/2/3237967.pd

SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

International audienceElectric devices should be resilient because reliability issues are increasingly problematic as technology scales down and the supply voltage is lowered. Specifically, the Soft-Error Rate (SER) increases due to the reduced feature size and the reduced charge. This paper describes an adaptive method to lower memory power using a dual Vdd in a column-based Vdd memory with Built-In Current Sensors (BICS). Using our method, we reduce the memory power by about 40% and increase the error immunity of the memory without the significant power overhead as in previous methods